 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| DATA SHEET MOS INTEGRATED CIRCUIT PD72850A IEEE1394 400Mbps PHY The PD72850A is the 3-port physical layer LSI which complies with the P1394a draft 2.0 specifications. The PD72850A works up to 400 Mbps. It is an upgrade of NEC's PD72850. FEATURES * The Three-port Physical Layer LSI complies to IEEE P1394a draft 2.0 * Connection debounce * Arbitration enhancements * Arbitrated short bus reset * Ack-accelerated arbitration * Fly-by concatenation * Multiple-speed packet concatenation * Arbitration enhancements and cycle start (controlled by the Link layer) * Performance optimization via PHY pinging * Priority arbitration (controlled by the Link layer) * Data rate: 393.216 / 196.608 / 98.304 Mbps * Compliant with Suspend/Resume function as defined in P1394a draft 2.1 * 3.3 V single power supply * Electrical isolated Link interface * 24.576 MHz crystal clock generation, 393.216 MHz PLL multiplying frequency * System power management by signaling of node power class information * Cable power monitor (CPS) is equipped * Fully interoperable with IEEE1394 std 1394 Link (FireWireTM, i.LINKTM) * Cable bias and terminal voltage driver supply function (for 3-port each) * Separate digital power and analog GND * Enable/Disable port control switch when power supply is powered on * Support Suspend/Resume Off mode (Compliant with P1394a draft 1.3) * Number of supported port are selectable * 1port, 2port, 3port. This selection is only under Suspend/Resume Off mode * Compliant with MD8405E (FUJIFILM MICRODEVICES CO., LTD) ORDERING INFORMATION Part number Package 80-pin plastic TQFP (Fine pitch) (12 x 12 mm) PD72850AGK-9EU The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S14452EJ1V0DS00 (1st edition) Date Published October 1999 NS CP(K) Printed in Japan 1999 PD72850A BLOCK DIAGRAM CMC PC0 PC1 PC2 PORTDIS PSEL SUS/RES LREQ LPS DIRECT SCLK LKON CTL0 CTL1 D0 D1 D2 D3 D4 D5 D6 D7 TpA0p TpA0n Cable Port1 TpB0p TpB0n Arbitration and Control State Machine Logic Cable Port2 Link Interface I/O Cable Port3 TpA1p TpA1n TpB1p TpB1n TpA2p TpA2n TpB2p TpB2n TpBias0 TpBias1 TpBias2 R0 R1 XI XO FIL0 FIL1 Receive Data Decoder and Retimer Voltage and Current Generator Crystal Oscillator PLL System and Transmit Clock Generator RESETB CPS Cable Power Status Transmit Data Encoder 2 Data Sheet S14452EJ1V0DS00 PD72850A PIN CONFIGURATION (Top View) * 80-pin plastic TQFP (Fine pitch) (12 x 12 mm) PC1 PC0 CMC DGND LPS LREQ DVDD DGND SCLK DVDD DGND CTL0 CTL1 DVDD D0 D1 DGND D2 D3 DGND 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 DVDD PC2 LKON DIRECT IC(H) IC(H) DGND AVDD AGND SUS/RES AGND AGND AGND AVDD PSEL AGND PORTDIS AVDD AGND AGND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 TpA0p TpA0n TpB0p TpB0n TpA1p TpA1n TpB1p TpB1n TpA2p TpA2n TpB2p TpB2n TpBias0 TpBias1 TpBias2 AVDD AGND CPS RI1 RI0 D4 D5 DGND D6 D7 DVDD DVDD DVDD DGND RESETB AVDD AGND AGND FIL1 FIL0 AVDD XI XO AGND AVDD Data Sheet S14452EJ1V0DS00 3 PD72850A PIN NAME AGND AVDD CMC CPS CTL0 CTL1 D0-D7 DGND Direct DVDD FIL0 FIL1 IC(H) LKON LPS LREQ PC0-PC2 PORTDIS PSEL RESETB RI0 RI1 SCLK SUS/RES TpA0n TpA0p TpA1n TpA1p TpA2n TpA2p TpB0n TpB0p TpB1n TpB1p TpB2n TpB2p TpBias0 TpBias1 TpBias2 XI XO : Analog GND : Analog Power : Configuration Manager Capable : Cable Power Status : Link Interface Control (bit 0) : Link Interface Control (bit 1) : Data Input/Output : Digital GND : PHY/Link Isolation Barrier Control Input : Digital VDD : APLL Filter Ground : APLL Filter : Internally Connected (High Clamped) : Link-on Signal Output : Link Power Status Input : Link Request Input : Power Class Set Input : Port Disable : Support Number of Port Select : Power on Reset Input : Reference Power Set, Connect Resistor 0 : Reference Power Set, Connect Resistor 1 : Link Control Output Clock : Suspend/Resume Function Select : First Port Twisted Pair Cable A Negative Phase I/O : First Port Twisted Pair Cable A Positive Phase I/O : Second Port Twisted Pair Cable A Negative Phase I/O : Second Port Twisted Pair Cable A Positive Phase I/O : Third Port Twisted Pair Cable A Negative Phase I/O : Third Port Twisted Pair Cable A Positive Phase I/O : First Port Twisted Pair Cable B Negative Phase I/O : First Port Twisted Pair Cable B Positive Phase I/O : Second Port Twisted Pair Cable B Negative Phase I/O : Second Port Twisted Pair Cable B Positive Phase I/O : Third Port Twisted Pair Cable B Negative Phase I/O : Third Port Twisted Pair Cable B Positive Phase I/O : First port Twisted Pair Output : Second Port Twisted Pair Output : Third Port Twisted Pair Output : Crystal Oscillator Connection XI : Crystal Oscillator Connection XO 4 Data Sheet S14452EJ1V0DS00 PD72850A CONTENTS 1. PIN 1.1 1.2 1.3 1.4 1.5 1.6 FUNCTIONS ..................................................................................................................................... 7 Cable Interface Pins......................................................................................................................... 7 Link Interface Pins ........................................................................................................................... 8 Control Pins...................................................................................................................................... 8 IC........................................................................................................................................................ 9 Power Supply Pins........................................................................................................................... 9 Other Pins......................................................................................................................................... 9 2. PHY REGISTERS ................................................................................................................................... 10 2.1 Complete Structure for PHY Registers ........................................................................................ 10 2.2 Port Status Page (Page 000) ......................................................................................................... 13 2.3 Vendor ID Page (Page 001) ........................................................................................................... 14 3. INTERNAL FUNCTION .......................................................................................................................... 15 3.1 Link Interface.................................................................................................................................. 15 3.1.1 Connection Method............................................................................................................................... 15 3.1.2 LPS (Link Power Status)....................................................................................................................... 15 3.1.3 LREQ, CTL0,CTL1, and D0-D7 Pins .................................................................................................... 15 3.1.4 SCLK..................................................................................................................................................... 15 3.1.5 LKON .................................................................................................................................................... 16 3.1.6 Direct .................................................................................................................................................... 16 3.1.7 Isolation Barrier..................................................................................................................................... 16 3.2 Cable Interface ............................................................................................................................... 18 3.2.1 Connections .......................................................................................................................................... 18 3.2.2 Cable Interface Circuit .......................................................................................................................... 19 3.2.3 Unused Ports ........................................................................................................................................ 19 3.2.4 CPS....................................................................................................................................................... 19 3.3 Suspend/Resume........................................................................................................................... 19 3.3.1 Suspend/Resume On Mode (SUS/RES = "H")...................................................................................... 19 3.3.2 Suspend/Resume Off Mode (SUS/RES = "L") ...................................................................................... 19 3.4 PLL and Crystal Oscillation Circuit.............................................................................................. 20 3.4.1 Crystal Oscillation Circuit...................................................................................................................... 20 3.4.2 PLL ....................................................................................................................................................... 20 3.5 PC0-PC2, CMC................................................................................................................................ 20 3.6 RESETB........................................................................................................................................... 20 3.7 RI1, RI0 ............................................................................................................................................ 20 4. PHY/LINK INTERFACE.......................................................................................................................... 21 4.1 Initialization of Link Power Status (LPS) and PHY/Link Interface............................................. 21 4.2 Link-on Indication .......................................................................................................................... 22 4.3 PHY/Link Interface Operation (CTL0, CTL1, LREQ, D0-D7) ....................................................... 23 4.3.1 CTL0,CTL1 ........................................................................................................................................... 23 4.3.2 LREQ .................................................................................................................................................... 23 4.3.3 PHY/Link Interface Timing .................................................................................................................... 27 4.4 Acceleration Control...................................................................................................................... 28 4.5 Transmit Status.............................................................................................................................. 29 5 Data Sheet S14452EJ1V0DS00 PD72850A 4.6 Transmit .......................................................................................................................................... 30 4.7 Cancel ............................................................................................................................................. 31 4.8 Receive............................................................................................................................................ 32 5. CABLE PHY PACKET............................................................................................................................ 33 5.1 Self_ID Packet ................................................................................................................................ 33 5.2 Link-on Packet ............................................................................................................................... 34 5.3 PHY Configuration Packet ............................................................................................................ 34 5.4 Extended PHY Packet .................................................................................................................... 34 5.4.1 Ping Packet........................................................................................................................................... 35 5.4.2 Remote Access Packet......................................................................................................................... 35 5.4.3 Remote Reply Packet ........................................................................................................................... 36 5.4.4 Remote Command Packet.................................................................................................................... 36 5.4.5 Remote Confirmation Packet ................................................................................................................ 37 5.4.6 Resume Packet..................................................................................................................................... 37 6. ELECTRICAL SPECIFICATIONS .......................................................................................................... 38 7. APPLICATION CIRCUIT EXAMPLE...................................................................................................... 43 7.1 IEEE1394 Interface ......................................................................................................................... 43 7.2 NEC/FFM Board Sharing ............................................................................................................... 44 8. PACKAGE DRAWING............................................................................................................................ 45 9. RECOMMENDED SOLDERING CONDITIONS ................................................................................... 46 6 Data Sheet S14452EJ1V0DS00 PD72850A 1. PIN FUNCTIONS 1.1 Cable Interface Pins Name TpA0p TpA0n TpB0p TpB0n TpA1p TpA1n TpB1p TpB1n TpA2p TpA2n TpB2p TpB2n PORTDIS 60 59 58 57 56 55 54 53 52 51 50 49 64 Pin No. I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I Function First port twisted pair cable A positive phase I/O First port twisted pair cable A negative phase I/O First port twisted pair cable B positive phase I/O First port twisted pair cable B negative phase I/O Second port twisted pair cable A positive phase I/O Second port twisted pair cable A negative phase I/O Second port twisted pair cable B positive phase I/O Second port twisted pair cable B negative phase I/O Third port twisted pair cable A positive phase I/O Third port twisted pair cable A negative phase I/O Third port twisted pair cable B positive phase I/O Third port twisted pair cable B negative phase I/O Port disable. SUS/RES(71pin)="1" This selected state will be loaded to Disabled bit which allocated PHY register Port Status Page when power-on reset. The PORTDIS pin is ignored except power-on reset. 1: All 3 ports will be disabled. 0: All 3 ports will be enabled. SUS/RES(71pin)="0" Combination with PSEL(66pin) input the supported number of port will be selected. Please refer to PSEL. PSEL 66 I Supported number of Port select (This function will be activated only under SUS/RES="0"). 64pin 1Port(Port0) 2Port(Port0,1) 3Port(Port0-2) 0 1 0 66pin 1 0 0 When SUS/RES="1", this pin should be connected to AGND. SUS/RES 71 I Suspend/Resume function select 1: Suspend/Resume on (P1394a draft 2.1 compliant) 0: Suspend/Resume off (P1394a draft 1.3 compliant) CPS 43 I Power cable status. Connect to the cable through a 390 k resistor. 0: Cable power fail 1: Cable power on Data Sheet S14452EJ1V0DS00 7 PD72850A 1.2 Link Interface Pins Name D0 D1 D2 D3 D4 D5 D6 D7 CTL0 CTL1 LREQ SCLK 15 16 18 19 21 22 24 25 12 13 6 9 Pin No. I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I O Data input/output (bit 0) Data input/output (bit 1) Data input/output (bit 2) Data input/output (bit 3) Data input/output (bit 4) Data input/output (bit 5) Data input/output (bit 6) Data input/output (bit 7) Link interface control (bit 0) Llink interface control (bit 1) Link request input Link control output clock LPS 1: 49.152 MHz output LPS 0: Clamp to 0 (The clock signal will be output within 25 sec after change to "0") LPS 5 I Link power status input 0: Link power off 1: Link power on (PHY/Link direct connection) Clock signal of about 300 kHz (if isolation) LKON 78 O Link-on signal output pin Link-on signal is 6.144 MHz clock output. Please refer to 4.2 Link-on Indication. Direct 77 I PHY/Link isolation barrier control input 0: Isolation barrier 1: PHY/Link direct connection Function 1.3 Control Pins Name PC0 PC1 PC2 CMC 2 1 79 3 Pin No. I/O I I I I Power class set input This pin status will be loaded to Pwr_class bit which allocated to PHY register 4H. IEEE1394-1995 chapter [4.3.4.1] Configuration manager capable setting. This pin status will be loaded to Contender bit which allocated to PHY register 4H. 0: Non contender 1: Contender RESETB 30 I Power on reset input. Connect to DGND through a 0.1 F capacitor. 0: Reset 1: Normal Function 8 Data Sheet S14452EJ1V0DS00 PD72850A 1.4 IC Name IC Pin No. 75, 76 I/O I Function Internally Connected (High Clamped) 1.5 Power Supply Pins Name AVDD Pin No. 31, 36 40, 45 63, 67, 73 AGND 32, 33 39, 44 61 62 65, 68-70, 72 DVDD 7, 10, 14, 26-28, 80 DGND 4, 8, 11, 17, 20, 23, 29, 74 Digital GND I/O Analog power 1 (APLL, OSC) Analog power 2 (Bias) Analog power 3 (Cable Interface) Analog GND1 (PLL, OSC) Analog GND2 (Bias) Analog GND3 (Common) Analog GND4 (Speed signal) Analog GND5 (Port) Digital VDD Function 1.6 Other Pins Name TpBias0 TpBias1 TpBias2 RI0 48 47 46 41 Pin No. I/O O O O First port twisted pair output Second port twisted pair output Third port twisted pair output Resistor connection pin0 for reference current generator. Please connect to RI1 pin via 9.1 k resistor. RI1 42 Resistor connection pin1 for reference current generator. Please connect to RI0 pin via 9.1 k resistor. FIL1 FIL0 XI XO 34 35 37 38 APLL filter (No need to assemble) APLL filter ground (No need to assemble) Crystal oscillator connection XI Crystal oscillator connection XO Function Data Sheet S14452EJ1V0DS00 9 PD72850A 2. PHY REGISTERS 2.1 Complete Structure for PHY Registers Figure 2-1. Complete Structure of PHY Registers 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Page_select Link_active Resume_int RHB IBR Extended (7) Max_speed Contender ISBR Loop Reserved Reserved Jitter Pwr_fail Timeout Port_event 1 2 Physical_ID Gap_count Total_ports Delay Pwr_class Enab_accel Enab_multi 3 4 5 6 R 7 PS Reserved Reserved Register0 (page_select) Register1 (page_select) Register2 (page_select) Register3 (page_select) Register4 (page_select) Register5 (page_select) Register6 (page_select) Register7 (page_select) Port_select 10 Data Sheet S14452EJ1V0DS00 PD72850A Table 2-1. Bit Field Description (1/2) Field Physical_ID R Size 6 1 R/W R R Reset value 000000 0 Description Physical_ID value selected from Self_ID period. If this bit is 1, the node is root. 1: Root 0: Not root PS 1 R Cable power status. 1: Cable power on 0: Cable power off RHB IBR 1 1 R/W R/W 0 0 Root Hold -off bit. If 1, becomes root at the bus reset. Initiate bus reset. Setting to 1 begins a long bus reset. Long bus reset signal duration: 166 sec. Returns to 0 at the beginning of bus reset. Gap_count 6 R/W 111111 Gap count value. It is updated by the changes of transmitting and receiving the PHY configuration packet Tx/Rx. The value is maintained after first bus reset. After the second bus reset it returns to reset value. Extended Total_ports 3 4 R R 111 0011 Shows the extended register map. Supported port number. When SUS/RES(71pin)="1" 0011 : 3 ports When SUS/RES(71pin)="0" Combination with PSEL(66pin) input the supported number of port will be selected. Please refer to 1.1 Cable Interface Pins. 0001 : 1 port 0010 : 2 port 0011 : 3 port Max_speed 3 R 010 Indicate the maximum speed that this node supports. 010: 98.304, 196.608 and 393.216 Mbps Delay Link_active 4 1 R R/W 0010 1 Indicate worst case repeating delay time. 144+(2 x 20)=184 nsec Link active. 1 : Enable 0 : Disable The logical AND status of this bit and LPS pin. State will be referred to "L bit" of Self-ID Packet#0. Contender 1 R/W See Description Contender. "1" indicate this node support bus manager function. This bit will be referred to "C bit" of Self-ID Packet#0. The reset data is depending on CMC pin setting. CMC pin condition 1: Pull up (Contender) 0: Pull down (Non Contender) Jitter 3 R 010 The difference of repeating time (Max.-Min.). (2+1) x 20=60 nsec Data Sheet S14452EJ1V0DS00 11 PD72850A Table 2-1. Bit Field Description (2/2) Field Pwr_class Size 3 R/W R/W Reset value See Description Description Power class. Please refer to IEEE1394 -1995 [4.3.4.1]. This bit will be referred to Pwr field of Self-ID Packet#0. The reset data will be determined by PC0-PC2 Pin status. Resume interrupt enable. When set to 1, if any one port does resume, the Port_event bit becomes 1. Initiate short (arbitrated) bus reset. Setting to 1 acquires the bus and begins short bus reset. Short bus reset signal output : 1.3 sec Returns to 0 at the beginning of the bus reset. Loop detection output. 1: Detection Writing 1 to this bit clears it to 0. Writing 0 has no effect. Power cable disconnect detect. It becomes 1 when there is a change from 1 to 0 in the CPS bit. Writing 1 to this bit clears it to 0. Writing 0 has no effect. Arbitration state machine time-out. Writing 1 to this bit clears it to 0. Writing 0 has no effect. Set to 1 when the Int_Enable bit in the register map of each port is 1 and there is a change in the ports connected, Bias, Disabled and Fault bits. Set to 1 when the Resume_int bit is 1 and any one port does resume. Writing 1 to this bit clears it to 0. Writing 0 has no effect. Enables arbitration acceleration. Ack-acceleration and Fly-by arbitration are enabled. 1: Enabled 0: Disabled If this bit changes while the bus request is pending, the operation is not guaranteed. Enable multi-speed packet concatenation. Setting this bit to 1 follows multi-speed transmission. When this bit is set to 0,the packet will be transmitted with the same speed as the first packet. Select page address between 1000 to 1111. 000: Port Status Page 001: Vendor Definition Page Others: Unused Port Selection. Selecting 000 (Port Status Page) with the page selection selects the port. 0000: Port 0 0001: Port 1 0010: Port 2 Others: Unused Reserved. Read as 0. Resume_int ISBR 1 1 R/W R/W 0 0 Loop 1 R/W 0 Pwr_fail 1 R/W 0 Timeout 1 R/W 0 Port_event 1 R/W 0 Enab_accel 1 R/W 0 Enab_multi 1 R/W 0 Page_select 3 R/W 000 Port_select 4 R/W 0000 Reserved - R 000... 12 Data Sheet S14452EJ1V0DS00 PD72850A 2.2 Port Status Page (Page 000) Figure 2-2. Port Status Page 0 1000 1001 1010 1011 1100 1101 1110 1111 AStat Negotiated_speed 1 2 BStat Int_enable 3 4 Child Fault 5 Connected 6 Bias Reserved 7 Disabled Reserved Reserved Reserved Reserved Reserved Reserved Table 2-2. Bit Field Description Field AStat Size 2 R/W R Reset value XX A port status value. 00:---, 10: "0" 01: "1", 11: "Z" BStat 2 R XX B port status value. 00:---, 10: "0" 01: "1", 11: "Z" Child 1 R Child node status value. 1: Connected to child node 0: Connected to parent node Connected 1 R 0 Connection status value. 1: Connected 0: Disconnected Bias 1 R Bias voltage status value. 1: Bias voltage 0: No bias voltage Disabled 1 R/W See Description Negotiated_ Speed 3 R The reset value is set by the PORTDIS pin. 1: Disable Shows the maximum data transfer rate of the node connected to this port. 000: 100 Mbps 001: 200 Mbps 010: 400 Mbps Int_enable 1 R/W 0 The Port_event is set to 1 by a change to 1 of the Connected, Bias, Disable, and Fault bits. Fault 1 R/W 0 Set to 1 if an error occurs during Suspend/Resume. Writing 1 to this bit clears it to 0. Writing 0 has no effect. Reserved R 000... Reserved. Read as 0. Description Data Sheet S14452EJ1V0DS00 13 PD72850A 2.3 Vendor ID Page (Page 001) Figure 2-3. Vendor ID Page 0 1000 1001 1010 1011 1100 1101 1110 1111 Product_ID Vendor_ID 1 2 3 4 5 6 7 Compliance_level Reserved Table 2-3. Bit Field Description Field Compliance_level Vendor_ID Product_ID Reserved Size 8 24 24 R/W R R R R 000... Reset value 00000001 00004CH According to IEEE P1394a. Company ID Code value, NEC IEEE OUI. Product code. Reserved. Read as 0. Description 14 Data Sheet S14452EJ1V0DS00 PD72850A 3. INTERNAL FUNCTION 3.1 Link Interface 3.1.1 Connection Method Figure 3-1. PHY/Link Connection Method D0-D7 CTL0,CTL1 LREQ SCLK LPS Link LKON PHY PD72850A DIRECT Note Note Clamping to VDD provides direct connection to Link. Clamping to GND connects through isolation barrier to Link. The isolation barrier connection circuit is described in 3.1.7 Isolation Barrier. 3.1.2 LPS (Link Power Status) LPS is a function to monitor the On/Off status of the Link power supply. After 1.2 sec or more, LPS is Low, the PHY/Link is reset and D and CTL are output Low (when the isolation barrier is Hi-Z). After 2.5 sec or more, LPS is Low, moreover, the PHY stops the supply of SCLK and SCLK outputs Low (when the isolation barrier is Hi-Z). 3.1.3 LREQ, CTL0,CTL1, and D0-D7 Pins LREQ D0-D7 : Indicates that a request is received from Link. : Bi-directional pin which controls the data Transfer/Receive status signal, and the speed code Transfer/Receive status signal. 3.1.4 SCLK 49.152 MHz clock supplied by PHY for the PHY/Link interface synchronization. CTL0,CTL1 : Bi-directional pin which controls the functions between the PHY/Link interface. Data Sheet S14452EJ1V0DS00 15 PD72850A 3.1.5 LKON When the Link power is off, it outputs a clock of 6.144 MHz. LKON outputs under the following conditions: LPS is Low and the internal PHY register of the Link_active bit is 0. * Link-on packet is received. * Any bit of Loop, Pwr_fail, Timeout or Port_event is the PHY internal register becomes 1, and moreover either LPS or Link_active bit is 0. When LPS is asserted, LKON returns to Low. 3.1.6 Direct Set Direct to Low for using the isolation barrier. 3.1.7 Isolation Barrier The IEEE1394 cable holds signals for Data/Strobe in addition to power and ground. When the ground potential is different between connecting devices, the DC and AC current flows through the ground line in the cable and there is a possibility of malfunction due to ground difference between the two PHY. The PD72850A uses the isolation barrier to couple the AC between the PHY/Link interface to overcome the ground difference problem. Connecting the Direct pin to Low enables the digital differential circuit of the PD72850A. The differential circuit propagates only the change in the signal; the interface will be driven only during transitions High Low or Low High. The interface will assume the high impedance state when there is no signal change. The PD72850A uses Schmitt trigger input buffers for D, CTL, LREQ and LPS pins to prevent noise when the bus assumes a high impedance state. The digital differential circuit and the Schmitt trigger input buffers are needed on the Link layer controller LSI to implement the isolation barrier. Figure 3-2. Waveforms of the Isolation Barrier Isolation Barrier not used 0 1 1 0 0 0 1 0 0 Using Isolation Barrier (Digital differential circuit) 0 1 Z 0 Z Z 1 0 Z 16 Data Sheet S14452EJ1V0DS00 PD72850A Figure 3-3. Isolation Barrier Circuits (a) CTL0,CTL1, D0-Dn Isolation Barrier Circuit LinkVDD Required when LinkVDD is 5 V DVDD PD72850A 5 k 0.001 F 5 k 300 LinkGND DGND Link 5 k 100 0.001 F 5 k LinkGND (b) Link-on Isolation Barrier Circuit Link 100 LinkVDD 5 k 0.001 F 1.6 k LinkGND PD72850A (c) LPS Isolation Barrier Circuit Link DVDD 8.4 k 10 k 0.033 F 1.6 k DGND PD72850A (d) LREQ Isolation Barrier Circuit Required when LinkVDD is 5 V Link LinkVDD 5k 100 0.001 F 5 k LinkGND DVDD 5 k 0.001 F 5 k 300 LinkGND DGND PD72850A (e) SCLK Isolation Barrier Circuit Link LinkVDD 5 k 0.001 F 5 k LinkGND 5 k DGND DVDD 5 k PD72850A Data Sheet S14452EJ1V0DS00 17 PD72850A 3.2 Cable Interface 3.2.1 Connections Figure 3-4. Cable Interface Connection Detection Current Connection Detection Comparator Common Mode Speed Current driver + Driver TpBias TpAp 7 k 7 k TpAn 56 56 56 56 TpBp 7 k 7 k TpBn Receiver + Arbitration Comparators + + Common Mode Comparator + Connection Detection Current Connection Detection Comparator Driver Receiver + Arbitration Comparators + + Common Mode Comparators + + - 1 F 0.01 F 5.1 k 270 pF Common Mode Speed Current Driver TpBias TpBp Driver 7 k 7 k TpBn Receiver + Arbitration Comparators + + Common Mode Comparator + 270 pF 5.1 k 0.01 F 1 F 56 56 56 56 TpAp 7 k 7 k TpAn + Driver Receiver + Arbitration Comparators + + Common Mode Comparators + + - 18 Data Sheet S14452EJ1V0DS00 PD72850A 3.2.2 Cable Interface Circuit Each port is configured with two twisted-pairs of TpA and TpB. TpA and TpB are used to monitor the state of the Transmit/Receive line, control signals, data and cables. During transmission to the IEEE1394 bus, the Data/Strobe signal received from the Link layer controller is encoded, converted from parallel to serial and transmitted. While receiving from the IEEE1394 bus, the Data/Strobe signal from TpA, TpB is converted from serial to parallel after synchronization by SCLK, then transmitted to the Link layer controller in 2/4/8 bits according to the data rate of 100/200/400 Mbps. The bus arbitration for TpA and TpB and the state of the line are monitored by the built-in comparator. The state of the IEEE1394 bus is transmitted to the state machine in the LSI. 3.2.3 Unused Ports TpAp, TpAn : Not connected TpBp, TpBn : AGND TpBias 3.2.4 CPS An external resistance of 390 k is connected in series to the power cable to monitor the power of the power cable. If the cable power falls under 7.5 V there is an indication to the Link layer controller that the power has failed. : Connected to AGND using a 1.0 F load capacitor 3.3 Suspend/Resume 3.3.1 Suspend/Resume On Mode (SUS/RES = "H") There are two ways of transition from the active status to the suspended status. One is when the receipt of a remote command packet that sets the initiate suspend command. After that, the PHY transmits a remote confirmation packet with the ok bit set, subsequently signals TX_SUSPEND to the connected peer PHY with the port which specified by the port field in the remote command packet, and then the PHY port transitions to the suspended state. The other is when the receipt of a RX_SUSPEND or RX_DISABLE_NOTIFY signal. When the port observes RX_SUSPEND, it transmits TX_SUSPEND to the active ports. The TX_SUSPEND transmitted propagates until it reaches a leaf node. The PHY port transitions to the suspended state. The propagation of the suspended domain may be blocked by a PHY compliant with IEEE Std 1394-1995, a disabled or a suspended port. Any one of a number of reasons may cause a suspended port to attempt to resume normal operations: * Bias is detected and there is no fault condition; * A resume packet is received or transmitted by the PHY; * A remote command packet that sets the resume port command is received; or * Either port of a node without active ports detects bias. 3.3.2 Suspend/Resume Off Mode (SUS/RES = "L") * Remote command packet is ignored. * Resume packet is ignored. * Disabled, Int_enable and resume_int bits in PHY register are ignored. * Responses to Remote access packet. * Detects the connection of the port in TpBias. Data Sheet S14452EJ1V0DS00 19 PD72850A 3.4 PLL and Crystal Oscillation Circuit 3.4.1 Crystal Oscillation Circuit To supply the clock of 24.576 MHz 100 ppm, use an external capacitor of 10 pF and a crystal of 50 ppm. 3.4.2 PLL The crystal oscillator multiplies the 24.576 MHz frequency by 16 (393.216 MHz). 3.5 PC0-PC2, CMC CMC shows the bus manager function which corresponds to the c bit of the Self_ID packet and the Contender bit in the PHY register when the input is High. The value of CMC can be changed with software through the Link layer; this pin sets the initial value during Poweron Reset. Use a pull-up or pull-down resistor of 10 k, based on the device's specification. The PC0-PC2 pin corresponds to the power field of the Self_ID packet and Pwr_class in the PHY register. Refer to Section 4.3.4.1 of the IEEE1394-1995 specification for information regarding the Pwr_class. The value of Pwr can be changed with software through the Link layer controller; this pin sets the initial value during Power-on Reset. Use a pull-up or pull-down resistor of 10 k based on the application. 3.6 RESETB Connect an external capacitor of 0.1 F between the pins RESETB and GND. If the voltage drops below 0 V, a reset pulse is generated. All of the circuits are initialized, including the contents of the PHY register. 3.7 RI1, RI0 Connect an external resistor of 9.1 k to limit the LSI's current. 20 Data Sheet S14452EJ1V0DS00 PD72850A 4. PHY/LINK INTERFACE 4.1 Initialization of Link Power Status (LPS) and PHY/Link Interface The LPS pin monitors the On/Off status of the Link power state. This pin is used during the PHY/Link interface Enable/Disable (initialization). Reset When the LPS input pin is Low for TLPS_RESET: * CTL0,CTL1 and D0-D7 output Low (When the isolation barrier is Hi-Z). * SCLK continuously supplies the clock signal to the Link. Disable When the LPS input pin is Low for TLPS_DISABLE: * CTL0,CTL1, D0-D7 continue to output Low as TLPS_RESET has already occurred (When the isolation barrier is Hi-Z). * SCLK to Link stops and it outputs Low (When the isolation barrier is Hi-Z). Table 4-1. LPS Timing Parameters Parameter LPS = Low propagation delay (with isolation barrier) LPS = High propagation delay (with isolation barrier) Reset active Disable active Setup time when using isolation barrier tLPSL tLPSH tLPS_RESET tLPS_DISABLE tRESTORE Symbol MIN. 0.09 0.09 1.2 25 15 MAX. 1.00 1.00 2.75 30 20 Unit s s s s s Figure 4-1. LPS Waveform when Connected to Isolation Barrier tLPSH tLPSL Data Sheet S14452EJ1V0DS00 21 PD72850A Figure 4-2. PHY/Link Interface Reset and Disable (a) D, CTL, LREQ LPS LPS (with isolation barrier) SCLK Reset tLPS_RESET tRESTORE (b) D, CTL, LREQ LPS LPS (with isolation barrier) SCLK Disable tLPS_DISABLE tRESTORE 4.2 Link-on Indication When the power supply of Link is off (LPS is Low and the internal PHY register Link_active bit is 0), the pin LKON outputs High according to the following conditions: (With isolation barrier, it outputs a clock of 6.144 MHz) * Link-on packet is received. * When any bit of the PD72850A PHY register's loop, Pwr fail, Timeout or Port_event becomes 1, and either LPS or the Link_active bit is 0. Table 4-2. Link-on Timing Parameter Frequency Duty Cycle Propagation delay before the Link becomes active (LPS is asserted and the Link_active bit in the PHY register is 1). MIN. 4 40 MAX. 8 60 500 Unit MHz % ns * If LPS or the Link_active bit is 0, the Link is considered inactive. When the Link is inactive and any of Loop, PWR_fail, Timeout, Port_event becomes 1, then Link-on is asserted High. * When the Link is active (both LPS and Link_active become 1) and Loop, Pwr_fail, Timeout and Port_event become 1, Status transfer is sent on the PHY/Link interface. 22 Data Sheet S14452EJ1V0DS00 PD72850A * The PD72850A activates the PHY/Link interface when LPS is 1, regardless of the value of the Link active bit. 4.3 PHY/Link Interface Operation (CTL0, CTL1, LREQ, D0-D7) The PHY/Link Interface consists of the following operations: * Status transfer to the Link layer controller by CTL * Transmit packet * Receive packet * Request from the Link layer controller by LREQ 4.3.1 CTL0,CTL1 CTL0,CTL1 controls the PHY/Link interface as shown in the Table 4-3. Table 4-3. CTL Controls PHY CTL0,CTL1 00 01 10 11 Idle Status Receive Grant Type PHY is in idle function PHY transmitting status information to Link PHY receiving data from the Link PHY allows Link to transmit data Content This is the operation by which, after Grant, the Link obtains the right to control the interface. Table 4-4. CTL Controls Link CTL0,CTL1 00 01 Idle Hold Type Content Link completes the packet transmission and releases the PHY/Link interface. 1) Link transmits Hold until the data is ready for transmission. 2) Link transmits the interface connect packet. 10 11 Transmit Link transmits the data to PHY. Not used. 4.3.2 LREQ Access to the PHY register and the bus is controlled from the Link layer controller through the LREQ pin of PHY. Figure 4-3. LREQ and CTL Timing LREQ LR0 LR1 LR2 LR3 L R (n-2) L R (n-1) CTL0,CTL1 CA CB C A : CTL before generation of LREQ C B : CTL during LREQ execution Data Sheet S14452EJ1V0DS00 23 PD72850A (1) LREQ format * Bus Request Table 4-5. Bus Request Format Bit 0 1-3 start request Type Signal that starts a request : 1 Bus request type: 000: ImmReq acknowledge packet transmit 001: IsoReq isochronous packet transmit 010: PriReq cycle start packet transmit 011: FairReq asynchronous packet transmit 4-6 speed Transmit speed: 000: 100 Mbps 010: 200 Mbps 100: 400 Mbps other: reserved 7 stop End request signal : 0 (optional) Content * PHY Register Read Request Table 4-6. Read Request Register Format Bit 0 1-3 start request Type Signal that starts a request : 1 Read Request. 100 : ReadReq 4-7 8 access address stop PHY register address. End request signal : 0 Content * PHY Register Write Request Table 4-7. Write Request Register Format Bit 0 1-3 start request Type Signal that starts a request : 1 Write Request. 101 : WriteReq 4-7 8-15 16 access address write data stop PHY register address. Write data. End request signal : 0 Content 24 Data Sheet S14452EJ1V0DS00 PD72850A * Acceleration Controller Table 4-8. Acceleration Controller Request Format Bit 0 1-3 4 start request access address Type Signal that starts a request : 1 110 : Acc Ctrl accelerate controller 0: Accelerate disable 1: Accelerate enable 5 stop End request signal : 0 Content Table 4-9. Request Type List Bit 000 ImmReq Type Content Used to acknowledge packet transmit. When Idle is detected, PHY immediately controls the bus. 001 IsoReq Used to transmit isochronous packet. PHY does arbitration after isochronous gap is detected and acquires the bus. 010 011 100 101 110 111 PriReq FairReq RdReg WrReg AccCtrl Used for Cycle master request. Fair request. PHY register read request. PHY register write request. Disable/enable of arbitration acceleration. Unused. For the Link to execute Priority request and Fair, start the request using LREQ when CTL0,CTL1 becomes idle, after one clock. When request is acknowledged, the PD72850A outputs Grant to CTL0,CTL1. The Link of cycle master uses PriReq to transmit the cycle start packet. IsoReq transmits the isochronous packet. IsoReq becomes effective only as follows: * The transmission of the cycle start packet is performed on the same isochronous period as Receive. (The period until the subaction gap is detected.) * During isochronous packet Transmit or Receive. The PD72850A cancels IsoReq with the subaction gap detection or bus reset. To meet the timing, do not issue the IsoReq to PHY when CRC operation is performed. The Link cancel method is described later. After the packet is received, Link issues ImmReq as the acknowledge packet transmission. The purpose is to prevent another node from detecting subaction gap as ACK_RESPONSE_TIME. The PD72850A acquires the bus after packet receive and returns Grant to CTL0,CTL1. When CRC fails, before Link detects Grant, assert 3 Idle cycles to CTL0,CTL1. When the bus reset is generated, the unprocessed requests are canceled. The PD72850A updates the data of the Write request register and the contents of the Read register are changed. The contents of the register of the specified address are output to the Link as a status transfer in the Read request register, When the status transmission is interrupted by transmitting/receiving packets, the status transmission will re-start from the first bit after completing the transmit/receive of the packets. Data Sheet S14452EJ1V0DS00 25 PD72850A The bus request (ImmReq, IsoReq, PriReg, FairReq) is completed (in case of ImmReq, IsoReq, when the subaction gap is detected) when the packet is transmitted or canceled by canceling the bus request. (2) LREQ rules The Link request and the status of the serial bus are asynchronous; the bus request can be canceled by the status of the serial bus. The following rules apply to a request by LREQ: * Link cannot issue a bus request (ImmReq, IsoReq, PriReq, FairReq) if Grant is given to an LREQ request or until the Link's request is canceled. The request can be canceled by the PD72850A if it detects subaction gap at ImmReq, IsoReq. * Do not issue a RdReg or WrReg request when the status transmission is not completed by the Read request register. * All of the bus requests (ImmReq, IsoReq, PriReq, FairReq) are canceled by a bus reset. In addition, there is a limitation in the request of LREQ according to the state of CTL as shown in Table 4-10. Table 4-10. Rules for Other Requests Request State of CTL in CA to which LREQ is allowed when PHY drives CTL Fair, Priority Idle, Status LREQ issues permission when Link drives CTL wrong Fair, Priority request cannot be issued until the unprocessed bus request is completed. Immediate Receive, Idle wrong Link issues the request after completing the decoding of Destination_ID, when the acknowledge packet is ready. After the packet is received, it is necessary to transmit the first bit of the request within four cycles. Isochronous any correct If the isochronous packet transmission is prepared for the isochronous period, it is issued. Do not issue the request to transmit the isochronous packet appending to the currently transmitted isochronous packet (Using Hold). Register Read Register Write AccCtrl any correct any correct Do not issue this request if the unprocessed Read request has not been completed. To set acceleration bit 0: When the isochronous period starts, if the Enab_accel bit is one, Cycle slave should adjust accelerate bit to 0. Note To set acceleration bit 1: Do not set the cycle master. It is issued when the isochronous period ends. 26 Data Sheet S14452EJ1V0DS00 PD72850A Table 4-11. PHY Operation Before LREQ Request to the CTL Function Changes Request State of CTL in C B after LREQ was issued Fair, Priority Receive * Hold the request if the acceleration of arbitration packet transmitted with enable is 8 bits (ACK). Except for 8 bits, the requests are ignored. * Ignore the request when the acceleration of arbitration is disabled. Grant Idle, Status Immediate Grant Receive Idle, Status Isochronous Transmit Idle (driven by Link) Grant Receive Status Idle Register Read Any (driven by Link) Grant Receive Status Idle Register Write, Acceleration control Any Request is completed. Request Hold. Request Hold. Hold the request until the corresponding register value is returned. The packet is being transmitted to Link. Request Hold. Excluding when the bus reset is generated, hold the request. Request Hold. Arbitration Won. Request Hold. Request is ignored when sub-action gap is detected. Arbitration Won. Excluding when the bus reset is generated, Hold the requests. Operation of the PHY (PD72850A) 4.3.3 PHY/Link Interface Timing (1) SCLK timing Table 4-12. SCLK Timing Timing Constant BUS_TO_LINK_DELAY Comment Period from receiving RX_DATA_PREFIX until Receive to CTL is output. DATA_PREFIX_TO_GRANT Period when the Grant is output to CTL after TX_DATA_PREFIX is output to a port. LINK_TO_BUS_DELAY Period when TX_DATA_END is output to all ports after transmitting the packet by Link after idle was asserted to CTL. MAX_HOLD Maximum period when Hold can be asserted by Link to confirm Grant. 47 SCLK cycle 2 5 SCLK cycle 25 SCLK cycle MIN. 2 MAX. 9 Unit SCLK cycle Data Sheet S14452EJ1V0DS00 27 PD72850A (2) AC timing Table 4-13. PHY/Link Interface Timing Parameter D, CTL propagation delay D, CTL, LREQ setup time D, CTL, LREQ Hold time Symbol tpd tsu th MIN. 0.5 6 0 MAX. 13.5 Unit ns ns ns Figure 4-4. PHY/Link Interface AC Timing SCLK tpd D, CTL tpd tpd SCLK tsu D, CTL, LREQ th 4.4 Acceleration Control Enable of ack-acceleration and fly-by on the same isochronous period may create a problem. The isochronous cycle may extend unintentionally when transmitting the asynchronous packet by a node using ack-acceleration and fly-by. To avoid this problem, Link should control Disable/Enable of these enhancements (ack-Acceleration, fly-by), by Acceleration Control requests. Cycle master cannot issue the Acceleration Control request. The enhancements should not be used from the generation of the local cycle synchronization event to the confirmation of cycle start. In this period, all Links except for Cycle Master use Acceleration Control as follows: * Do not issue Fair nor Priority request to Link after generating local cycle synchronization, if the Acceleration Control request's Accelerate bit is not set to 0. * Link must not use Hold when transmitting continuous primary asynchronous packet after the Acknowledge packet, except after ack_pending to complete the split transaction. * Ending the Link during the isochronous period issues the acceleration control request to set the Accelerate bit to 1, enabling these enhancements. The PD72850A does not require setting the Acceleration Control during isochronous transmit to enable the isochronous request fly-by acceleration. It is not necessary to issue Acceleration Control request when the cycle master is absent from the serial bus. These enhancements are enabled if the Enab_accel bit in the PHY register is set. The PD72850A supports Variable Acceleration controlled by the Acceleration Control during power-on reset. 28 Data Sheet S14452EJ1V0DS00 PD72850A 4.5 Transmit Status Pin D0,D1 of the PD72850A transmits status information to the Link. Status is asserted to CTL while transmitting Status. The status transmission is interrupted if the serial bus receives a packet which contains states other than status to CTL. Between two status transmissions, assert Idle to CTL for at least one SCLK cycle. The PD72850A transmits status in 16 bits as follows: * In response to the register request * After deciding the new Physical_ID for the Self_ID period resetting the bus (after a Self_ID packet is transmitted) The event indication is the only 4-bit transmission of the PD72850A. Figure 4-5. Status Timing PHY CTL0,CTL1 00 01 01 01 S14, S15 00 00 PHY D0-D7 00 S0,S1 S2,S3 00 00 Table 4-14. Status Data Format Bit(s) 0 1 2 3 Name ARB_RESET_GAP SUBACTION_GAP BUS_RESET_START Phy_interrupt Arbitration Reset gap detect Subaction gap detect Bus reset detect Either of the following states is detected: * The topology of the bus is a loop * Voltage drop on the power cable * Arbitration state machine timeout * Port Event 4-7 8-15 Address Data PHY register address Register data Description The bits already transmitted are set to 0. Example If the status transmission is interrupted after S0,S1 bit was transmitted, then in the next status transfer, S0,S1 becomes 0. Therefore one of the following situations will occur when the PD72850A re-transmits status after an interruption of the status transmission: * At least one bit of S0-S3 is 1 * The PHY register data contains the interrupt status information The status transmission always begins with S0,S1. If the Link executes read request, and Subaction gap and arbitration reset gap are detected, priority is given to the transmission of gap status, postponing the response to the register read request. Data Sheet S14452EJ1V0DS00 29 PD72850A 4.6 Transmit The PD72850A arbitrates the serial bus using Link's LREQ. * When the PD72850A acquires the bus, a Grant period of 1 SCLK is executed to CTL0,CTL1. After that, an Idle period of 1 SCLK cycle is executed. * Link controls the interface executing Idle, Hold of Transmit to CTL0,CTL1 after 1 SCLK cycle when Grant from PHY is detected. * Before asserting Hold and Transmit, assert 1 Idle cycle. Do not execute Idle for 2 or more cycles. * If the packet transmit is not ready, the Hold period can be extended up to MAX_HOLD. * The PD72850A outputs DATA_PREFIX to the serial bus while Hold is being asserted to CTL. * When the packet transmit is ready, Link outputs the first bit of the packet and Transmit is asserted to CTL at the same time. * After transmitting the last bit of the packet, Link outputs for Idle or Hold to CTL for 1 cycle. After that, it outputs Idle for 1 cycle. When PHY/Link releases the bus, output Low to CTL and D0-D7 within 1 cycle. Figure 4-6. Transmit Timing (a) Single Packet PHY CTL0,CTL1 00 11 00 ZZ ZZ ZZ ZZ ZZ ZZ ZZ ZZ ZZ ZZ 00 PHY D0-D7 00 00 00 ZZ ZZ ZZ ZZ ZZ ZZ ZZ ZZ 00 Link CTL0,CTL1 ZZ ZZ ZZ 00 01 01 10 10 10 10 00 00 ZZ Link D0-D7 ZZ ZZ ZZ 00 00 00 D0 D1 D2 Dn 00 00 ZZ (b) Concatenated Packet PHY CTL0,CTL1 ZZ ZZ ZZ ZZ 00 00 11 00 ZZ ZZ ZZ ZZ ZZ PHY D0-D7 ZZ ZZ ZZ ZZ 00 00 00 00 ZZ ZZ ZZ ZZ ZZ Link CTL0,CTL1 10 10 01 00 ZZ ZZ ZZ ZZ 00 00 01 01 10 10 Link D0-D7 D n-1 Dn SP 00 ZZ ZZ ZZ ZZ 00 00 D0 D1 Note In case of packet transmission after Grant, before actual transmission, Hold does not need to be asserted. Link can transmit continuous packets without releasing the bus. * Hold is asserted to CTL. This function is used when the Link transmits continuous packets after acknowledge and isochronous packets. Link outputs the transfer rate signal of the following packet to D0-D7 and asserts Hold simultaneously. * After Hold is detected by MIN_PACKET_SEPARATION, the PD72850A outputs Grant to CTL. 30 Data Sheet S14452EJ1V0DS00 PD72850A * Link controls the interface by generating Idle, Hold or Transmit to CTL0,CTL1, after 1 SCLK cycle when Grant from PHY is detected. * Assert 1 Idle cycle before asserting Hold and Transmit (do not output 2 or more Idle cycles). When the packet transmission is not ready, assert Hold. The Hold output period after Grant is detected should not exceed the period provided by MAX_HOLD. The following limitations exist though Link can transmit the concatenated packet with a different transfer rate. Link cannot transmit other than S100 connecting packets after S100 (concatenated) packets have been transmitted. A new request to transmit must be issued in order to transmit S100 packets at a transfer rate of S200 or more. If the En_Multi bit in the PHY register is 0, the PD72850A assumes the same speed as the first packet, for all of the concatenated packets. At the end of packet transmission, Link asserts Idle to CTL for a period of 2 cycles. After sampling Idle from Link, the PD72850A asserts Idle to CTL for a period of 1 cycle. 4.7 Cancel This section describes how Link operates, when after the bus has been acquired by the request of LREQ, there is no data transmission. In this case, a Null packet with no data is transmitted to the serial bus (DATA_PREFIX DATA_END). Following are two method for canceling the Link: 1. As explained in Section 4.6, the Link outputs Idle or Hold, then outputs Transmit to CTL after confirming Grant. Here, the Link asserts Idle for two cycles to CTL, then switches to high impedance. The PD72850A confirms Cancel at the second Idle cycle. To prevent the bus from switching to high impedance, a third Idle cycle is needed. Figure 4-7. Link Cancel Timing (After Grant) PHY CTL0,CTL1 00 11 00 ZZ ZZ ZZ ZZ 00 PHY D0-D7 00 00 00 ZZ ZZ 00 Link CTL0,CTL1 ZZ ZZ ZZ 00 00 00 ZZ Link D0-D7 ZZ ZZ ZZ 00 00 00 ZZ 2. To cancel after asserting Hold, assert Idle between two cycles; it switches to high impedance. This method cancels the packet transmission connection (concatenated) after Grant is received. The PD72850A cancels with the next Idle cycle of Hold. To prevent CTL from switching to high impedance, assert a second Idle cycle. Data Sheet S14452EJ1V0DS00 31 PD72850A Figure 4-8. Link Cancel Timing (After Hold) PHY CTL0,CTL1 00 11 00 ZZ ZZ ZZ ZZ ZZ ZZ 00 PHY D0-D7 00 00 00 ZZ ZZ ZZ ZZ 00 Link CTL0,CTL1 ZZ ZZ ZZ 00 01 01 00 00 ZZ Link D0-D7 ZZ ZZ ZZ 00 00 00 00 00 ZZ 4.8 Receive This section shows the operation when the packet is received from the serial bus. * When the PD72850A detects DATA_PREFIX on the serial bus, it asserts receive to CTL and all of the D pins assume the logic value of 1. * The PD72850A shows the speed code of the transfer rate ahead of the packet using bits D0-D7. Transmitting the speed code with the speed signal is the protocol of the PHY/Link interface. The speed code is not included in the CRC calculation. * The PD72850A continues to assert Receive to CTL until the packet is finally transmitted. * Idle is asserted to CTL, indicating completion of the packet transmission. Figure 4-9. Receive Timing PHY CTL0,CTL1 (Binary) PHY D0-D7 (Hex) 00 10 10 10 10 10 10 00 00 00 FF FF SP D0 D1 Dn 00 00 The packet transfer rate of the serial bus depends on the topology of the bus. The PD72850A checks if the node can receive at the faster transfer rate. At this time, DATA_PREFIX DATA_END is transmitted to the PD72850A. After DATA_PREFIX is transmitted to the Link, Receive from the serial bus is completed, asserting Idle. Table 4-15 shows the speed code encoding. Table 4-15. Speed Encoding D0-D7 Transmitted 00000000 01000000 01010000 11111111 Observed 00xxxxxx 0100xxxx 01010000 11xxxxxxxx S100 S200 S400 Data Prefix Data rate 32 Data Sheet S14452EJ1V0DS00 PD72850A 5. CABLE PHY PACKET The node on the serial bus transmits and receives the PHY packet to control the bus. The PHY packet is composed of 2 quadlets (64-bit); the second quadlet (32-bit) contains the inverse value of the first quadlet. The PHY packet is transmitted at a transfer rate of S100. All of the PHY packets received from the serial bus are transmitted to the Link. Though the PHY packet from the PD72850A is transmitted to the Link, the PHY packet which was transmitted from the Link of the node is not transmitted to the Link. There are four types of PHY packets, as follows: * Self_ID packet * Link-on packet * PHY configuration packet * Extended PHY packet The Self_ID packet transmitted automatically by the PD72850A is also transmitted to the Link of a local node. The PD72850A PHY packet Receive from the serial bus operates similar to the PHY packet transmitted by the Link (when the packet transmission to the Link is executed). 5.1 Self_ID Packet During the Self_ID phase of the initialization or when the Ping packet responds, the PD72850A transmits the Self_ID packet. Figure 5-1. Self_ID Packet Format 10 phy_ID 0 L gap_cnt sp rsv c pwr p0 p1 p2 i m Logical Inverse of the first quadlet Table 5-1. Self_ID Packet Field phy_ID L gap_cnt sp c pwr Physical ID of the node. Logical product of Link_active and LPS in the PHY register. Gap_count value in the PHY register. Physpeed 10 (corresponds to 98.304, 196.608, 393.216 Mbps). C bit values in the PHY register. pwr value in the PHY register. 000: The node does not need the power supply. No power repeat. 001: Obtains power supply for the node. Can supply 15W or more. 010: Obtains power supply for the node. Can supply 30W or more. 011: Obtains power supply for the node. Can supply 45W or more. 100: The node consumes 3W maximum power. 110: The node consumes 3W maximum power. At least 3W are necessary to enable Link. 111: The node consumes 3W maximum power. At least 7W are necessary to enable Link. i m rsv It shows that the node issued Bus Reset and the bus was reset. Read as 0. Read as 00. Description Data Sheet S14452EJ1V0DS00 33 PD72850A 5.2 Link-on Packet The PD72850A outputs the Link-on signal of 6.144 MHz from the pin LKON when receiving the Link-on packet. Figure 5-2. Link-on Packet Format 01 phy_ID 0000 0000 0000 0000 0000 0000 Logical Inverse of the first quadlet Table 5-2. Link-on Packet Field phy_ID Description Physical_ID of the destination of the Link-on packet 5.3 PHY Configuration Packet Use the PHY configuration packet to set the gap count for the bus. Figure 5-3. PHY Configuration Packet Format 00 root_ID R T gap_cnt 0000 0000 0000 0000 Logical Inverse of the first quadlet Table 5-3. PHY Configuration Packet Field root_ID R Description Sets the Physical_ID node as root contender (for the next reset). When this bit is set to 1 and the Phyisical_ID of the node corresponds to the rootID of this packet, the PD72850A sets the force_root bit. The force_root bit is cleared if there is discrepancy. T If this bit is 1, the gap_cnt value of this packet is used as the gap_count value. The gap_count value must not be cleared by the following bus reset, set the gap_count_reset_disable flag in the PD72850A to TRUE. gap_cnt When this packet is received, the gap count is set to this value. While it remains effective for the next bus reset, it will be cleared by the second bus reset to 3FH. Remark Applying 0 to both R,T, regards the following packets as extended PHY packets, the PHY configuration is not recognized. 5.4 Extended PHY Packet An extended PHY packet is defined when both the R (in the PHY configuration packet) and T bits are transmitted as 0. The extended PHY packet does not influence the force_root_bit and the gap_count bit on any node. Following are the types of extended PHY packets: * Ping packet * Remote access packet * Remote reply packet * Remote command packet * Remote confirmation packet * Resume packet 34 Data Sheet S14452EJ1V0DS00 PD72850A 5.4.1 Ping Packet When the PD72850A receives the Ping packet, it will transmit the Self_ID packet within the RESPONSE_TIME. Figure 5-4. Ping Packet Format 00 phy_ID 00 type (0) 00 0000 0000 0000 0000 Logical Inverse of the first quadlet Table 5-4. Ping Packet Field phy_ID type Description Physical ID of the destination node of the Ping packet Indicates that there is a Ping packet with a value of 0 5.4.2 Remote Access Packet The Remote access packet reads information in the PHY register of another node. The PHY specified by the Remote access packet transmits the value in the register using the Remote Reply packet. Figure 5-5. Remote Access Packet Format 00 phy_ID 00 type page port reg reserved Logical Inverse of the first quadlet Table 5-5. Remote Access Packet Field phy_ID type page port reg Description Physical ID of the destination node of the Remote access packet 1 = read register (base register), 5 = read register (page register) Specifies the page of the PHY register Specifies the register of each port in the PHY register Specifies the address when reading the base register. In case of the Page and port registers, specifies the address with 1000+reg. Data Sheet S14452EJ1V0DS00 35 PD72850A 5.4.3 Remote Reply Packet The PD72850A transmits the value in the register by using the Remote reply packet as a response to the Remote access packet. Figure 5-6. Remote Reply Packet Format 00 phy_ID 00 type page port reg data Logical Inverse of the first quadlet Table 5-6. Remote Reply Packet Field phy_ID type page port reg Description Physical ID of the node (Node's original packet transmit) 3 = register read (base register), 7 = read register (page register) Used when specifying the page of the PHY register Used to specify the register of each port in the PHY register Specifies the address when reading the base register. In case of the Page and port registers, specify the address with 1000+reg. data Contents of the specified register 5.4.4 Remote Command Packet Use the Remote command packet to operate the function of the port of the PHY of another node. Figure 5-7. Remote Command Packet Format 00 phy_ID 00 type(8) 000 port 0000 0000 cmnd Logical Inverse of the first quadlet Table 5-7. Remote Command Packet Field phy_ID type port cmnd Physical ID of the destination packet Extended PHY packet type; set to 8 for Remote command packet Port of the PHY of the operating node Command 0: NOP 1: Disables the port after transmission of the TX_DISABLE_NOTIFY 2: Suspend initiator 4: Clears to 0 the Fault bit of the port 5: Enables the port 6: Resumes the port Description 36 Data Sheet S14452EJ1V0DS00 PD72850A 5.4.5 Remote Confirmation Packet The PD72850A transmits the Remote confirmation when the Remote command packet is received, responding whether Cmnd can be executed. Figure 5-8. Remote Confirmation Packet Format 00 phy_ID 00 type(A16) 000 port 000 f c b d ok cmnd Logical Inverse of the first quadlet Table 5-8. Remote Confirmation Packet Field phy_ID type port f c b d ok cmnd Description Physical ID of the node (node's original packet transmit) Extended PHY packet type; set to A16 for Remote confirmation packet Port set from the Remote command packet Fault bit value of the PHY register of this port Connected bit value of the PHY register of this port Bias bit value of the PHY register of this port Disable bit value of the PHY register of this port 1 indicates executing; otherwise it is 0 Specifies the command value with the Remote command packet 5.4.6 Resume Packet When the PD72850A receives the Resume packet, all of the ports that were suspended resume the connection. The Resume packet does the broadcast. Figure 5-9. Resume Packet Format 00 phy_ID 00 type (F16) 00 0000 0000 0000 0000 Logical Inverse of the first quadlet Table 5-9. Resume Packet Field phy_ID type Physical ID of the original packet transmit Extended PHY packet type; set to F16 for Resume packet Description Data Sheet S14452EJ1V0DS00 37 PD72850A 6. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Parameter Power supply voltage Input voltage Output voltage Storage temperature Symbol VDDm VIN VOUT Tstg Condition Rating -0.5 to +4.6 -0.5 to VDD+0.5 -0.5 to VDD+0.5 -40 to +125 Unit V V V C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Ranges Parameter Power supply voltage Operating temperature Power dissipation Symbol VDD TA PD Condition MIN. 3.0 0.0 TYP. 3.3 MAX. 3.6 70.0 0.9 Unit V C W 38 Data Sheet S14452EJ1V0DS00 PD72850A DC Characteristics Common Parameter Supply current Symbol IDD Condition 3-port, S400, VDD = 3.6 V 1-port transmit or receive, S400, VDD = 3.3 V 135 MIN. TYP. MAX. 240 Unit mA mA PHY/Link Interface Parameter High-level output voltage (Undifferentiated) High-level output voltage (Differentiated) Low-level output voltage (Undifferentiated) Low-level output voltage (Differentiated) High-level input voltage (Undifferentiated) Low-level input voltage (Undifferentiated) Input rising threshold voltage (LPS) Input falling threshold voltage (LPS) Symbol VOH VOHD VOL VOLD VIH VIL VLIT+ VLITVLREF +0.2 Hysteresis input rising threshold voltage(Differentiated) Hysteresis input falling threshold voltage(Differentiated) Reference voltage Reference voltage (LPS) Input capacitance VREF VLREF CIN 0.5 VITVIT+ VREF +0.3 VREF -0.9 VDD/21% 1.6 7.5 VREF +0.9 VREF -0.3 V V pF V V Condition IOH = -4 mA IOH = -9 mA IOH = 4 mA IOH = 9 mA 2.6 MIN. 2.8 VDD-0.4 0.4 0.4 VDD+10% 0.7 VLREF+1 TYP. MAX. Unit V V V V V V V V Cable Interface Parameter Differential input voltage Symbol VID Condition Cable input, 100 Mbps operation Cable input, 200 Mbps operation Cable input, 400 Mbps operation TpB common mode input voltage VICM 100 Mbps speed signaling off 200 Mbps speed signaling 400 Mbps speed signaling Differential output voltage TpA common mode output voltage VOD VOCM Cable output (Test load 55) 100 Mbps speed signaling off 200 Mbps speed signaling 400 Mbps speed signaling TpA common mode output current ICM 100 Mbps speed signaling off 200 Mbps speed signaling 400 Mbps speed signaling Power status threshold voltage TpBias output voltage VTH VTPBIAS CPS 1.665 MIN. 142 132 118 1.165 0.935 0.523 172.0 1.665 1.438 1.030 -0.81 -4.84 -12.40 TYP. MAX. 260 260 260 2.515 2.515 2.515 265.0 2.015 2.015 2.015 +0.44 -2.53 -8.10 7.5 2.015 Unit mV mV mV V V V mV V V V mA mA mA V V Data Sheet S14452EJ1V0DS00 39 PD72850A AC Characteristics PHY/Link Interface Parameter D, CTL, LREQ setup time D, CTL, LREQ hold time D, CTL output timing SCLK cycle time SCLK high level time SCLK low level time LKON cycle time Symbol tSU tHD tD tSCLK tSCLKH tSCLKL tLINKON Condition MIN. 6 0 2 20 9 9 160 11 11 12 TYP. MAX. Unit ns ns ns ns ns ns ns Link Interface Timing (SCLK, LKON) SCLK tSCLKH tSCLK tSCLKL LKON tLINKON 40 Data Sheet S14452EJ1V0DS00 PD72850A Link Interface Timing (CTL, D) SCLK tD Transmit CTL0,CTL1 tD tD tD D0-D7 tD tD tSU Receive CTL0,CTL1 tSU tH tH D0-D7 Link Interface Timing (LREQ) SCLK tSU tH LREQ Data Sheet S14452EJ1V0DS00 41 PD72850A Cable Interface Parameter TpA, TpB transfer jitter TpA strobe, TpB data transfer TPA, TPB rise time/fall time Symbol tJITTER tSKEW tR/tF Condition Between TpA and TpB Between TpA and TpB 10% to 90%, via 55 and 10 pF MIN. TYP. MAX. 0.15 0.10 1.2 Unit ns ns ns 42 Data Sheet S14452EJ1V0DS00 0.1 F 7.1 IEEE1394 Interface 0.1 F 7. APPLICATION CIRCUIT EXAMPLE Note 0.1 F 22 F 56 56 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 AGND AGND AVDD PORTDIS AGND PSEL AVDD AGND AGND AGND SUS/RES AGND AVDD DGND IC(H) IC(H) DIRECT LKON PC2 DVDD 0.01 F 5.1 k 270 pF 0.01 F 5.1 k 270 pF 0.01 F 5.1 k 270 pF 1.0 F 1.0 F 1.0 F 0.1 F 390 k Note Note Note Common mode choke. Recommendation : TOKO 1 2 3 4 56 56 56 56 56 56 56 56 56 56 0.1 F PC1 PC0 CMC DGND TpA0p TpA0n TpB0p TpB0n 60 59 58 57 0.1 F Part No.857CM-0009 (TYPE B5W) Data Sheet S14452EJ1V0DS00 0.1 F VP (Cable Supply Voltage) 0.1 F 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 AVDD AGND XO XI AVDD FIL0 FIL1 AGND AGND AVDD RESETB DGND DVDD DVDD DVDD D7 D6 DGND D5 D4 0.1 F 10 pF 10 pF 0.1 F LPS LREQ DVDD DGND SCLK DVDD DGND CTL0 CTL1 DVDD D0 D1 DGND D2 D3 DGND TpA1p TpA1n TpB1p TpB1n TpA2p TpA2n TpB2p TpB2n TpBias0 TpBias1 TpBias2 AVDD AGND CPS RI1 RI0 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 9.1 k ( 0.5 %) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 0.1 F 0.1 F 0.1 F VPOWER (3.3 V) 33 F Digital GND 0.1 F 0.1 F 0.1 F 33 F Analog GND 33 F PD72850A Analog GND 43 PD72850A 7.2 NEC/FFM Board Sharing 0.1 F AVDD + 22 F AGND 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 MD8405E 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 AGND 0.33 F 0.33 F 0.33 F Vp 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1.8 k 2.7 k AVDD 33 pF 0.1 F 18 k 220 k 11 k 220 pF 0.1 F 510 620 AVDD + 22 F AGND AGND MD8405E (FUJIFILM MICRODEVICED CO.,LTD) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PD72850A 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 AGND 1 . 0 F 1 . 0 F 1 . 0 F Vp 390 k AVDD 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 9.1 k AGND 44 Data Sheet S14452EJ1V0DS00 PD72850A 8. PACKAGE DRAWING 80-PIN PLASTIC TQFP (FINE PITCH) (12x12) A B 60 61 41 40 detail of lead end S C D Q R 80 1 20 21 F G H P I M J K S N S L M NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 14.00.2 12.00.2 12.00.2 14.00.2 1.25 1.25 0.220.05 0.10 0.5 (T.P.) 1.00.2 0.50.2 0.1450.05 0.10 1.00.05 0.10.05 3 +7 -3 1.2 MAX. S80GK-50-9EU-1 Data Sheet S14452EJ1V0DS00 45 PD72850A 9. RECOMMENDED SOLDERING CONDITIONS The PD72850A should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 9-1. Surface Mounting Type Soldering Conditions PD72850AGK-9EU : 80-pin plastic TQFP (Fine pitch) (12 x 12 mm) Soldering Method Infrared reflow Package peak temperature: 235C, Time: 30 sec. Max. (at 210C or higher). Count: three times or less Exposure limit: 3 daysNote (after that prebake at 125C for 10 hours) Partial heating Pin temperature: 300C Max., Time: 3 sec. Max. (per pin row) -- Soldering Conditions Recommended Condition Symbol IR35-103-3 Note After opening the dry pach, store it at 25C or less and 65% RH or less for the allowable storage period. 46 Data Sheet S14452EJ1V0DS00 PD72850A NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S14452EJ1V0DS00 47 PD72850A FireWire is a trademark of Apple Computer, Inc. i.LINK is a trademark of Sony Corporation. The export of this product from Japan is prohibited without governmental license. To export or re-export this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. * The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98. 8 |
Price & Availability of UPD72850A
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |